Datasheet

Section 6 Bus Controller (BSC)
Page 174 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name Initial Value R/W Description
12 CAST 0 R/W Column Address Output Cycle Number Select
Selects whether the column address output cycle
in DRAM access comprises 3 states or 2 states.
The setting of this bit applies to all areas
designated as DRAM space.
0: Column address output cycle comprises
2 states
1: Column address output cycle comprises
3 states
11 ⎯ 0 R/W Reserved
This bit can be read from or written to. However,
the write value should always be 0.