Section 6 Bus Controller (BSC)
Page 168 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
T
h
Address
φ
T
1
T
2
T
3
T
t
Bus cycle
Data
HWR, LWR
Write
Data
RD
CS
Read
Figure 6.3 CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0)
