Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 167 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the T
h
cycle is to
be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
one-state T
h
cycle, in which only the CSn and
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (T
h
) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (T
h
) is extended
(n = 7 to 0)
• CSACRL
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the T
t
cycle
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state T
t
cycle, in which only the
CSn and address signals are asserted, is inserted
after the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (T
t
) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (T
t
) is extended
(n = 7 to 0)