Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 153 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
CS7 to CS0
WAIT
BREQ
BACK
BREQO
ABWCR ASTCR
WTCRAH WTCRAL
WTCRBH WTCRBL
RDNCR
MPXCR
DRAMCR
DRACCRH
DRACCRL
REFCR
RTCNT RTCOR
CSACRH CSACRL
BROMCRH BROMCRL
BCR
Area decoder
Internal address bus
EXDMAC address bus
External bus
control signals
Internal bus control signals
Internal data bus
Control registers
Address
selector
External bus
arbiter
External bus controller
Internal bus
arbiter
Internal bus controller
Internal bus master bus request signal
EXDMAC bus request signal*
Internal bus master bus acknowledge signal
EXDMAC bus acknowledge signal*
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
[Legend]
ABWCR: Bus width control register
ASTCR: Access state control register
WTCRAH, WTCRAL,
WTCRBH, and WTCRBL: Wait control registers AH, AL, BH, and BL
RDNCR: Read strobe timing control register
CSACRH and CSACRL: CS assertion period control registers H and L
BROMCRH: Area 0 burst ROM interface control register
BROMCRL : Area 1 burst ROM interface control register
BCR: Bus control register
MPXCR: Address/data multiplexed I/O control register
DRAMCR: DRAM control register
DRACCRH and DRACCRL: DRAM access control registers H and L
REFCR: Refresh control register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
Note: * Not supported in the H8S/2454 Group.
Figure 6.1 Block Diagram of Bus Controller