Datasheet

Section 5 Interrupt Controller
R01UH0309EJ0500 Rev. 5.00 Page 131 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
5.5 Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector
Address
*
1
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode IPR Priority
DTC
Activation
DMAC
Activation
NMI 7 H'001C ⎯ High ⎯ ⎯
IRQ0 16 H'0040 IPRA14 to IPRA12
⎯
IRQ1 17 H'0044 IPRA10 to IPRA8 ⎯
IRQ2 18 H'0048 IPRA6 to IPRA4 ⎯
IRQ3 19 H'004C IPRA2 to IPRA0 ⎯
IRQ4 20 H'0050 IPRB14 to IPRB12 ⎯
IRQ5 21 H'0054 IPRB10 to IPRB8 ⎯
IRQ6 22 H'0058 IPRB6 to IPRB4 ⎯
IRQ7 23 H'005C IPRB2 to IPRB0 ⎯
IRQ8*
2
24 H'0060 IPRC14 to IPRC12 ⎯
IRQ9*
2
25 H'0064 IPRC10 to IPRC8 ⎯
IRQ10*
2
26 H'0068 IPRC6 to IPRC4 ⎯
IRQ11*
2
27 H'006C IPRC2 to IPRC0 ⎯
IRQ12*
2
28 H'0070 IPRD14 to IPRD12 ⎯
IRQ13*
2
29 H'0074 IPRD10 to IPRD8 ⎯
IRQ14*
2
30 H'0078 IPRD6 to IPRD4 ⎯
External pin
IRQ15*
2
31 H'007C IPRD2 to IPRD0 ⎯
DTC SWDTEND 32 H'0080 IPRE14 to IPRE12 ⎯
WDT WOVI0 33 H'0084 IPRE10 to IPRE8 ⎯ ⎯
⎯ Reserved for
system use
34 H'0088 IPRE6 to IPRE4
Low
⎯ ⎯