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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 32 MHz I/O number 96
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Section 5 Interrupt Controller
R01UH0309EJ0500 Rev. 5.00 Page 129 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
5.4 Interrupt Sources
5.4.1 External Interrupts
The H8S/2456 Group and H8S/2456R Group each have seventeen external interrupts: NMI and
IRQ15 to IRQ0. The H8S/2454 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These
interrupts can be used to restore the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQn Interrupts (n = 0 to 15 for H8S/2456 Group and H8S/2456R Group, n = 0 to 7 for
H8S/2454 Group): An IRQn interrupt is requested by an input signal at the IRQn pin. The IRQn
interrupts have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at the IRQn pin.
• Enabling or disabling of IRQn interrupt requests can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of IRQn interrupt requests is indicated in ISR. ISR flags can be cleared to 0 by
software.
When IRQn interrupt requests occur at low level of the IRQn pin, the corresponding IRQ pin
should be held low until an interrupt handling starts. Then the corresponding IRQ pin should be
set to high in the interrupt handling routine and clear the IRQnF bit in ISR to 0. Interrupts may not
be executed when the corresponding IRQ pin is set to high before the interrupt handling starts.
Detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or
output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
A block diagram of IRQn interrupts is shown in figure 5.2.