Datasheet

Section 5 Interrupt Controller
Page 124 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
5.3.5 IRQ Status Register (ISR)
ISR is an IRQ15 to IRQ0 interrupt request flag register.
Bit Bit Name Initial Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRQ15F*
2
IRQ14F*
2
IRQ13F*
2
IRQ12F*
2
IRQ11F*
2
IRQ10F*
2
IRQ9F*
2
IRQ8F*
2
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
[Setting condition]
When the interrupt source selected by ISCR
occurs
[Clearing conditions]
• Cleared by reading IRQnF flag when IRQnF =
1, then writing 0 to IRQnF flag
• When interrupt exception handling is executed
when low-level detection is set and IRQn input
is high
• When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
• When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the DTC
is cleared to 0
Notes: 1. Only 0 can be written, to clear the flag.
2. These bits are reserved in the H8S/2454 Group.