Datasheet

Page 1402 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Data transfer controller (DTC) ............... 477
Data transfer instructions.......................... 64
DMA controller (DMAC)....................... 321
DMTEND0A .......................................... 133
DMTEND0B .......................................... 133
DMTEND1A .......................................... 133
DMTEND1B .......................................... 133
DRAM interface ............................. 209, 223
DTC vector table .................................... 487
Dual address mode.................................. 424
E
Effective address extension ...................... 72
Ending DMA transfer ............................. 471
ERI0........................................................ 939
ERI1........................................................ 134
ERI2........................................................ 134
ERI3........................................................ 134
ERI4........................................................ 134
Exception handling................................... 97
Exception handling vector table ............... 98
EXDMA controller (EXDMAC) ............ 407
EXDMTEND2........................................ 134
EXDMTEND3........................................ 134
Extended register (EXR) .......................... 56
Extension of chip select (CS)
assertion period............................... 208, 221
External request mode ............................ 428
F
Flash Memory....................................... 1145
Framing error.......................................... 901
Full-scale error...................................... 1086
G
General Call Address............................ 1035
General registers....................................... 55
I
I/O Port States in Each Processing
State ...................................................... 1359
I/O ports.................................................. 509
I
2
C Bus Format ..................................... 1037
I
2
C Bus Interface (IIC).......................... 1021
Idle cycle................................................. 290
Idle mode ................................................ 358
IICI0................................................ 135, 136
IICI1................................................ 135, 136
immediate ................................................. 76
Input capture function............................. 748
Input pull-up MOS.................................. 509
Instruction set............................................ 62
Interrupt control modes........................... 138
Interrupt exception handling................... 104
Interrupt exception handling vector
table ........................................................ 131
Interrupt mask bit...................................... 57
interrupt mask level .................................. 56
Interrupt priority register (IPR)............... 109
Interrupt sources ..................................... 401
Interrupt-in transfer............................... 1007
Interval timer mode................................. 854
IrDA operation........................................ 935
IRQ0 ....................................................... 131
L
List of Registers.................................... 1237
Logic operations instructions.................... 67
M
Mark state ............................................... 942
MCU operating modes.............................. 83
memory indirect........................................ 77
Multi-channel operation.......................... 395
Multiply-accumulate register (MAC) ....... 58