Datasheet

R01UH0309EJ0500 Rev. 5.00 Page 1399 of 1408
Sep 24, 2012
Item Page Revision (See Manual for Details)
Table 26.17 DC
Characteristics (1)
1307,
1308
Amended and added
Item
Schmitt trigger input
voltage
Ports 1*
6
and 2*
6
,
P32 to P35*
2
,
P50 to P53*
2
,
port 8*
2
, PA4 to
PA7*
2
, ports B*
2
and C*
2
, PF1*
2
,
PF2*
2
, P81*
2
and P83*
2
Input high voltage P10 to P11*
5
,
P14 to P17*
5
,
P25*
5
,P26*
5
,
port 3*
3
,
P50 to P53*
3
,
port 8*
3
, ports A
to G*
3
Input low voltage P10 to P11*
5
,
P14 to P17*
5
,
P24*
6
, P26*
6
,
ports 3*
3
,
and 5*
3
, port 8,*
3
ports A to G*
3
Notes: 5. When used as SSO, SSI, SSCK, SCS, WAIT, ADTRG1 or
DREQ.
6. When used as other than SSO, SSI, SSCK, SCS, WAIT,
ADTRG1 or DREQ.
Table 26.24 Timing of
On-Chip Peripheral
Modules
1318 Amended
Item Symbol Min.
Master 4 Clock cycle
Slave
tSUcyc
4
Master 48 Clock high pulse
width
Slave
tHI
48
Master 48
SSU*
Clock low pulse
width
Slave
t
LO
48