Datasheet

Page 1394 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Item Page Revision (See Manual for Details)
• PF0/WAIT-A/
ADTRG0-B/
SCS0-C/OE-A
(H8S/2454 Group)
• Modes 3 and 7
(EXPE = 0)
667 Notes amended
3. When using as SCS0-C input, set SCS0S1 and SCS0S0 in
PFCR5 to B'10 before other register setting.
4. When using as SCS0-C output, set SCS0S1 and SCS0S0 in
PFCR5 to B'10 before other register setting.
5. When using as SCS0-C input/output, set SCS0S1 and
SCS0S0 in PFCR5 to B'10 before other register setting.
15.3.7 Serial Status
Register (SSR)
Smart Card Interface
Mode (When SMIF bit
in SCMR is 1)
881 Amended
Bit Bit Name Description
2 TEND Timing to set this bit differs according to the register
settings.
GM = 0, BLK = 0: 12.5 etu after transmission
GM = 0, BLK = 1: 11.5 etu after transmission
GM = 1, BLK = 0: 11.0 etu after transmission
GM = 1, BLK = 1: 11.0 etu after transmission
Table 15.2
Relationships between
N Setting in BRR and
Bit Rate B
883 Amended and added
Bit Rate
N =− 1
64 × 2
2n−1
× B
φ × 10
6
− 1N =
32 × 2
2n−1
× B
φ × 10
6
− 1N =
8 × 2
2n−1
× B
φ × 10
6
− 1N =
S × 2
2n+1
× B
φ × 10
6
Table 16.1 Pin
Configuration
950 Amended
Pin Name I/O
PUPD+ Output