Datasheet

Appendix
R01UH0309EJ0500 Rev. 5.00 Page 1377 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
Software
Standby Mode
Bus Release
State
Program
Execution State
Sleep Mode
PG3/CS3/
RAS3
PG2/CS2/
RAS2
PG1/CS1
1, 2, 3, 4, 7 T T [CS output,
OPE = 0]
T
[CS output,
OPE = 1]
H
[Other than the
above]
Keep
[CS output]
T
[Other than the
above]
Keep
[CS output]
CS
[Other than the
above]
I/O port
1, 2 H PG0/CS0
3, 4, 7 T
T [CS output,
OPE = 0]
T
[CS output,
OPE = 1]
H
[Other than the
above]
Keep
[CS output]
T
[Other than the
above]
Keep
[CS output]
CS
[Other than the
above]
I/O port
WDTOVF 1, 2, 3, 4, 7 H H H H H*
USD+, USD− 1, 2, 3, 4, 7 T T T Keep USD+, USD−
[Legend]
H: High-level
L: Low-level
Keep: Input ports become high-impedance, and output ports retain their state.
T: High-impedance
DDR: Data direction register
OPE: Output port enable
Note: * Low output if a watchdog timer overflow occurs when WT/IT is 1.