Datasheet

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6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 318
6.15.4 BREQO Output Timing........................................................................................ 319
6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 319
Section 7 DMA Controller (DMAC)................................................................. 321
7.1 Features.............................................................................................................................. 321
7.2 Input/Output Pins...............................................................................................................323
7.3 Register Descriptions......................................................................................................... 324
7.3.1 Memory Address Registers (MARA and MARB)................................................ 326
7.3.2 I/O Address Registers (IOARA and IOARB)....................................................... 327
7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 328
7.3.4 DMA Control Registers (DMACRA and DMACRB) .......................................... 329
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 337
7.3.6 DMA Write Enable Register (DMAWER) ........................................................... 348
7.3.7 DMA Terminal Control Register (DMATCR) ..................................................... 350
7.4 Activation Sources............................................................................................................. 351
7.4.1 Activation by Internal Interrupt Request .............................................................. 352
7.4.2 Activation by External Request ............................................................................ 353
7.4.3 Activation by Auto-Request ................................................................................. 353
7.5 Operation ........................................................................................................................... 353
7.5.1 Transfer Modes..................................................................................................... 353
7.5.2 Sequential Mode ................................................................................................... 356
7.5.3 Idle Mode.............................................................................................................. 358
7.5.4 Repeat Mode......................................................................................................... 361
7.5.5 Single Address Mode............................................................................................ 365
7.5.6 Normal Mode........................................................................................................ 368
7.5.7 Block Transfer Mode ............................................................................................ 371
7.5.8 Basic Bus Cycles .................................................................................................. 377
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles................................................ 378
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 387
7.5.11 Write Data Buffer Function .................................................................................. 394
7.5.12 Multi-Channel Operation...................................................................................... 395
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and
EXDMAC............................................................................................................. 397
7.5.14 DMAC and NMI Interrupts .................................................................................. 398
7.5.15 Forced Termination of DMAC Operation ............................................................ 399
7.5.16 Clearing Full Address Mode................................................................................. 400
7.6 Interrupt Sources................................................................................................................ 401
7.7 Usage Notes ....................................................................................................................... 402