Datasheet

Section 26 Electrical Characteristics
R01UH0309EJ0500 Rev. 5.00 Page 1337 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3
φ
A23 to A0
RAS5 to RAS0
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
t
RCH
t
RCS2
t
AC8
t
CPW2
D15 to D0
AS
Read
Write
DACK and EDACK timing: when DDS = 1 and EDDS = 1
RAS timing: when RAST = 1
Note:
DACK0, DACK1
EDACK2, EDACK3
Figure 26.19 DRAM Access Timing: Three-State Burst Access