Datasheet

Section 4 Exception Handling
Page 106 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
4.7 Illegal Instruction Exception Handling
Illegal instruction exception handling starts when the CPU executing an illegal instruction code is
detected. Illegal instruction exception handling can be executed at all times in the program
execution state.
The illegal instruction exception handling is as follows:
1. The values in the PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the exception is generated, the
start address of the exception service routine is loaded from the vector table to the PC, and
program execution starts from that address.
Table 4.5 shows the status of CCR and EXR after execution of illegal instruction exception
handling.
Table 4.5 Status of CCR and EXR after Illegal Instruction Exception Handling
CCR EXR
Interrupt Control Mode I UI T I2 to I0
0 1 ⎯ ⎯ ⎯
2 1 ⎯ 0 ⎯
[Legend]
1: Set to 1
0: Cleared to 0
⎯: Retains value prior to execution
Illegal instruction codes will not be searched for in the fields that do not affect instruction
definitions, such as the EA extension or register fields. Instruction codes for an instruction formed
with several words are detected independently, and combined instruction codes are not detected.
Undefined instruction codes must not be executed. The general register contents after execution of
an undefined instruction code or illegal instruction exception handling cannot be guaranteed. The
stack pointer during illegal instruction exception handling and the PC value that will be saved are
also not guaranteed.