Datasheet

Section 26 Electrical Characteristics
Page 1318 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Item Symbol Min. Max. Unit Test Conditions
A/D
converter
Trigger input setup time t
TRGS
30 ⎯ ns Figure 26.49
IIC2 SCL input cycle time t
SCL
12 t
cyc
+600 ⎯ ns Figure 26.50
SCL input high pulse width t
SCLH
3 t
cyc
+300 ⎯ ns
SCL input low pulse width t
SCLL
5 t
cyc
+300 ⎯ ns
SCL, SDA Input falling time t
Sf
⎯ 300 ns
IIC2 SCL, SDA Input spike pulse
removal time
t
SP
⎯ 1 t
cyc
ns Figure 26.50
SDA input bus free time t
BUF
5 t
cyc
⎯ ns
Start condition input hold
time
t
STAH
3 t
cyc
⎯ ns
Retransmit start condition
input setup time
t
STAS
3 t
cyc
⎯ ns
Stop condition input setup
time
t
STOS
3 t
cyc
⎯ ns
Data input setup time t
SDAS
1 t
cyc
+20 ⎯ ns
Data input hold time t
SDAH
0 ⎯ ns
SCL, SDA capacitive load Cb ⎯ 400 PF
SCL, SDA falling time t
Sf
⎯ 300 ns
Master 4 256 t
cyc
SSU* Clock cycle
Slave
t
SUcyc
4 256
Figures 26.51 to
26.54
Master 48 ⎯ Clock high pulse
width
Slave
t
HI
48 ⎯
ns
Master 48 ⎯ Clock low pulse
width
Slave
t
LO
48 ⎯
ns
Clock rising time t
RISE
⎯ 20 ns
Clock falling time t
FALL
⎯ 20 ns
Master 25 ⎯ Data input setup
time
Slave
t
SU
30 ⎯
ns
Master 10 ⎯ Data input hold
time
Slave
t
H
10 ⎯
ns
Master 2.5 ⎯ SCS setup time
Slave
t
LEAD
2.5 ⎯
t
cyc