Datasheet

Section 26 Electrical Characteristics
R01UH0309EJ0500 Rev. 5.00 Page 1297 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Item Symbol Min. Max. Unit Test Conditions
Counter address read data access time 2 t
AA2
⎯ 1.5 × t
cyc
− 25 ns
Counter address read data access time 3 t
AA3
⎯ 2.0 × t
cyc
− 25 ns
Counter address read data access time 4 t
AA4
⎯ 2.5 × t
cyc
− 25 ns
Counter address read data access time 5 t
AA5
⎯ 3.0 × t
cyc
− 25 ns
Counter address read data access time 6 t
AA6
⎯ 4.0 × t
cyc
− 25 ns
Multiplexed address delay time t
MAD
⎯ 20 ns
Multiplexed address setup time 1 t
MAS1
0.5 × t
cyc
− 15 ⎯ ns
Multiplexed address setup time 2 t
MAS2
1.5 × t
cyc
− 15 ⎯ ns
Multiplexed address hold time t
MAH
1.0 × t
cyc
− 15 ⎯ ns
AH delay time t
AHD
⎯ 15 ns
Figures 26.8 to
26.23, 26.29, and
26.30
Table 26.8 Bus Timing (2)
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 8 MHz to 33 MHz
Item Symbol Min. Max. Unit Test Conditions
WR delay time 1 t
WRD1
⎯ 15 ns
WR delay time 2 t
WRD2
⎯ 15 ns
WR pulse width 1 t
WSW1
1.0 × t
cyc
−13 ⎯ ns
Figures 26.8 to
26.23, 26.29, and
26.30
WR pulse width 2 t
WSW2
1.5 × t
cyc
−13 ⎯ ns
Write data delay time t
WDD
⎯ 23 ns
Write data setup time 1 t
WDS1
0.5 × t
cyc
−15 ⎯ ns
Write data setup time 2 t
WDS2
1.0 × t
cyc
−15 ⎯ ns
Write data setup time 3 t
WDS3
1.5 × t
cyc
−15 ⎯ ns
Write data hold time 1 t
WDH1
0.5 × t
cyc
−13 ⎯ ns
Write data hold time 2 t
WDH2
1.0 × t
cyc
−13 ⎯ ns
Write data hold time 3 t
WDH3
1.5 × t
cyc
−13 ⎯ ns
Write command setup time 1 t
WCS1
0.5 × t
cyc
−10 ⎯ ns
Write command setup time 2 t
WCS2
1.0 × t
cyc
−10 ⎯ ns
Write command hold time 1 t
WCH1
0.5 × t
cyc
−10 ⎯ ns
Write command hold time 2 t
WCH2
1.0 × t
cyc
−10 ⎯ ns
Read command setup time 1 t
RCS1
1.5 × t
cyc
−10 ⎯ ns
Read command setup time 2 t
RCS2
2.0 × t
cyc
−10 ⎯ ns