Datasheet

Section 4 Exception Handling

R01UH0309EJ0500 Rev. 5.00 Page 101 of 1408

Sep 24, 2012

H8S/2456, H8S/2456R, H8S/2454 Group

RES

High

Vector fetch

Internal

processing

Prefetch of first

program instruction

(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)

(2)(4) Start address (contents of reset exception handling vector address)

(5) Start address ((5)=(2)(4))

(6) First program instruction

Internal

address bus

Internal read

signal

Internal write

signal

Internal data

bus

(1)

(2) (4) (6)

(3) (5)

Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)