Datasheet

Page xiii of xxx
6.7.10 Byte Access Control ............................................................................................. 236
6.7.11 Burst Operation..................................................................................................... 238
6.7.12 Refresh Control..................................................................................................... 244
6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 252
6.8 Synchronous DRAM Interface........................................................................................... 255
6.8.1 Setting Continuous Synchronous DRAM Space................................................... 255
6.8.2 Address Multiplexing ........................................................................................... 256
6.8.3 Data Bus ............................................................................................................... 257
6.8.4 Pins Used for Synchronous DRAM Interface....................................................... 257
6.8.5 Synchronous DRAM Clock.................................................................................. 259
6.8.6 Basic Timing......................................................................................................... 259
6.8.7 CAS Latency Control............................................................................................ 261
6.8.8 Row Address Output State Control....................................................................... 263
6.8.9 Precharge State Count........................................................................................... 264
6.8.10 Bus Cycle Control in Write Cycle ........................................................................ 266
6.8.11 Byte Access Control ............................................................................................. 267
6.8.12 Burst Operation..................................................................................................... 270
6.8.13 Refresh Control..................................................................................................... 274
6.8.14 Mode Register Setting of Synchronous DRAM.................................................... 281
6.8.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous
DRAM Interface ................................................................................................... 282
6.9 Burst ROM Interface.......................................................................................................... 287
6.9.1 Basic Timing......................................................................................................... 287
6.9.2 Wait Control ......................................................................................................... 289
6.9.3 Write Access......................................................................................................... 289
6.10 Idle Cycle........................................................................................................................... 290
6.10.1 Operation .............................................................................................................. 290
6.10.2 Pin States in Idle Cycle......................................................................................... 309
6.11 Write Data Buffer Function ............................................................................................... 310
6.12 Bus Release........................................................................................................................ 311
6.12.1 Operation .............................................................................................................. 311
6.12.2 Pin States in External Bus Released State ............................................................ 312
6.12.3 Transition Timing ................................................................................................. 313
6.13 Bus Arbitration .................................................................................................................. 315
6.13.1 Operation .............................................................................................................. 315
6.13.2 Bus Transfer Timing............................................................................................. 316
6.14 Bus Controller Operation in Reset ..................................................................................... 318
6.15 Usage Notes ....................................................................................................................... 318
6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 318
6.15.2 External Bus Release Function and Software Standby ......................................... 318