Datasheet

Section 25 List of Registers
Page 1238 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
25.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name Abbreviation
Number
of Bits Address Module
Data
Width
Access
States
DTC mode register A MRA 8 DTC 16/32 2
DTC source address register SAR 24 DTC 16/32 2
DTC mode register B MRB 8 DTC 16/32 2
DTC destination address register DAR 24 DTC 16/32 2
DTC transfer count register A CRA 16 DTC 16/32 2
DTC transfer count register B CRB 16
H'BC00 to
H'BFFF
DTC 16/32 2
Interrupt flag register 0 IFR0 8 H'FB00 USB 8 3
Interrupt flag register 1 IFR1 8 H'FB01 USB 8 3
Interrupt flag register 2 IFR2 8 H'FB02 USB 8 3
Interrupt enable register 0 IER0 8 H'FB08 USB 8 3
Interrupt enable register 1 IER1 8 H'FB09 USB 8 3
Interrupt enable register 2 IER2 8 H'FB0A USB 8 3
Interrupt select register 0 ISR0 8 H'FB10 USB 8 3
Interrupt select register 1 ISR1 8 H'FB11 USB 8 3
Interrupt select register 2 ISR2 8 H'FB12 USB 8 3
EP0i data register EPDR0i 32 H'FB20 USB 8 3
EP0o data register EPDR0o 32 H'FB24 USB 8 3
EP0s data register EPDR0s 32 H'FB28 USB 8 3
EP1 data register EPDR1 32 H'FB30 USB 8 3
EP2 data register EPDR2 32 H'FB34 USB 8 3
EP3 data register EPDR3 32 H'FB38 USB 8 3
EP0o receive data size register EPSZ0o 8 H'FB80 USB 8 3
EP1 receive data size register EPSZ1 8 H'FB81 USB 8 3
Data status register 0 DASTS0 8 H'FB88 USB 8 3
Data status register 1 DASTS1 8 H'FB89 USB 8 3
Trigger register 0 TRG0 8 H'FB90 USB 8 3
Trigger register 1 TRG1 8 H'FB91 USB 8 3