Datasheet

Section 24 Power-Down Modes
Page 1236 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
24.5.6 Notes on Clock Division Mode
The following points should be noted in clock division mode.
• Select the clock division ratio by the STC1 and STC0 bits so that the frequency of φ is within
the operation guaranteed range of clock cycle time tcyc shown in the Electrical Characteristics.
In other words, the frequency of φ must be 8 MHz or higher; be careful not so specify φ < 8
MHz.
• All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, the wait time for clearing software standby mode differs by changing the clock
division ratio.
• Note that the frequency of φ will be changed by changing the clock division ratio.