Datasheet

Section 24 Power-Down Modes
R01UH0309EJ0500 Rev. 5.00 Page 1231 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
24.2.5 Module Stop Function
Module stop function can be set for individual on-chip peripheral modules.
When an MSTP bit in MSTPCR, EXMSTPCR, or RMMSTPCR is set to 1, the corresponding
module stops operation at the end of the bus cycle and a transition is made to module stop state.
The CPU continues operating independently.
When an MSTP bit is cleared to 0, the corresponding module stop state is cleared and the module
starts operating at the end of the bus cycle. In module stop state, part of SCI registers and the
internal state of SSU are reset but the internal states of the other modules are retained.
After reset clearance, all modules other than the EXDMAC*, DMAC, DTC, and on-chip RAM are
in module stop state.
The module registers that are set in module stop state cannot be read or written to.
The module-stop function for RAM is only effective for on-chip RAM. When an area of on-chip
RAM is set up as an external address space by bits RAME and EXPE in SYSCR, the resulting
external space is accessible regardless of the module-stop setting. Table 24.3 lists the kinds of
operation in case of access to the on-chip RAM area.
Note: * The EXDMAC is not supported by the H8S/2454 Group.
Table 24.3 Combinations of SYSCR Settings and Operation in Access to On-Chip RAM
Register Settings
RAME EXPE mstp Target for Access Description
1 ⎯ This area is not readable/writable and access is
prohibited.
1 X
0 On-chip RAM
1 X External address
space
0
0 X ⎯ This area is not readable/writable and access is
prohibited.