Datasheet

Section 3 MCU Operating Modes
R01UH0309EJ0500 Rev. 5.00 Page 95 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
H'000000
H'FEC000
H'FFC000
H'FFD000
External address space
Internal I/O registers
External address space
Internal I/O registers
H'FFFFFF
H'FFFA00
H'FFFF00
H'FFFF20
H'FE8000
RAM: 64 Kbytes
/48 Kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
External address
space
Reserved area
*
2
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. A reserved area should not be accessed.
Reserved area
*
2
H'FF0000
O n-chip RAM/External address space*
1
*
3
3. Area from H'FEC000 to H'FEFFFF in the H8S/24561, H8S/24561R, and H8S/24541 Groups is
reserved and should not be accessed.
On-chip RAM/External address space/
Reserved area
*
1
*
3
Figure 3.5 Memory Map in Each Operating Mode (ROM-Less Version):
H8S/24562, H8S/24562R, H8S/24561, H8S/24561R, H8S/24542, and H8S/24541