Datasheet

Section 23 Clock Pulse Generator
Page 1210 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
23.4 PLL Circuit for the USB Module
The PLL circuit for the USB module takes 8, 12, and 16 MHz clock signals from an oscillator and
generates the 48-MHz clock for the USB module through frequency-multiplication by 3, 4, or 6.
The frequency-multiplication factor is set by bits USSTC1 and USSTC0 in the USPLLCR. For
details on the USPLLCR, see section 23.1.3, USB PLL Control Register (USPLLCR).
When the USB is in use, make settings so that the system clock runs at or above 14 MHz. The
settings listed below (table 23.4) produce a USB dedicated clock at 48 MHz. Operation at other
frequencies cannot be guaranteed.
Table 23.4 Clock Selection when the USB is to be used
Input clock frequency
from the oscillator (MHz)
USB dedicated clock
(cku: 48 MHz) System clock (φ)
8 MHz EXTAL × 6 EXTAL × 2 (16MHz)
12 MHz EXTAL × 4 EXTAL × 2 (24MHz)
EXTAL × 2 (32MHz) 16 MHz EXTAL × 3
EXTAL × 1 (16MHz)