Datasheet

Section 23 Clock Pulse Generator
R01UH0309EJ0500 Rev. 5.00 Page 1201 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 23 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and
internal clocks. The clock pulse generator consists of an oscillator circuit, a system-clock PLL
circuit and a divider.
Figure 23.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
PLLCR
USSTC0, USSTC1
USPLLCR
Oscillator
System-clock
PLL circuit
(×1, 2)
PLL circuit
for USB
(×3, 4, 6)
STC0, STC1
USB dedicated clock to USB
Divider
System clock
to φ pin
Internal clock
to peripheral
modules
[Legend]
PLLCR: PLL control register
USPLLCR: PLL control register for USB
Figure 23.1 Block Diagram of Clock Pulse Generator
The frequency of the system clock from the oscillator can be changed by means of the system-
clock PLL circuit and divider. Frequency changes are made by software by means of settings in
the PLL control register (PLLCR).
The USB module requires a 48-MHz clock. Set the frequency of the USB dedicated clock (cku toe
48 MHz. Changes to the frequency of the USB dedicated clock are made by software by means of
settings in the USB PLL control register (USPLLCR).