Datasheet

Section 22 Flash Memory
Page 1186 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
The calculated operating frequency should be checked to ensure that it is within the range of
minimum to maximum frequencies which are available with the clock modes of the specified
device. When it is out of this range, an operating frequency error is generated.
4. Bit rate
To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR),
and the value (N) in the bit rate register (BRR), which are found from the peripheral operating
clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than
4%. If the error is 4% or more, a bit rate error is generated. The error is calculated using the
following expression:
Error (%) = {[ ] − 1} × 100
(N + 1) × B × 64 × 2
(2×n − 1)
φ × 10
6
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
Confirmation H'06
• Confirmation, H'06, (1 byte): Confirmation of a new bit rate
Response H'06
• Response, H'06, (1 byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 22.13.
Host
Boot program
Setting a new bit rate
H'06 (ACK)
Waiting for one-bit period
at the specified bit rate
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
Setting a new bit rate
Setting a new bit rate
Figure 22.13 New Bit-Rate Selection Sequence