Datasheet

Section 22 Flash Memory
Page 1156 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
22.4.1 Read Array
This command reads the flash memory.
Write H'FFxx in the first bus cycle to shift the flash memory into the read array mode. Specify the
target read address in the next bus cycle after setting the CBIDB bit in FLMCR1 to 1, and data is
read from the address in 16-bit units.
As the flash memory stays in the read array mode until another command is issued, multiple
addresses can be read in sequence.
22.4.2 Read Status Register
This command reads the status register.
Write H'70xx in the first bus cycle, and the status register can be read in the second bus cycle (see
section 22.5, Status Register). Specify an even address in the user ROM, data flash, or user boot
ROM to read the status register.
Do not issue this command in the EW1 mode.
22.4.3 Clear Status Register
This command clears the status register.
Write H'50xx in the first bus cycle, and the FMERSF and FMPRSF bits in FLMSTR are cleared to
0.
22.4.4 Program
This command writes data to the flash memory in 2-word units.
Write H'41xx in the first bus cycle and write data to the target address in the second and third bus
cycles; the flash memory starts automatic writing (programming and verifying data). The address
value specified in the first bus cycle should be the same even address as that specified in the
second bus cycle.
Completion of automatic writing can be checked through the FMRDY bit in FLMSTR. The
FMRDY bit is 0 (busy) during automatic writing and becomes 1 (ready) when writing is
completed.