Datasheet

Section 20 Synchronous Serial Communication Unit (SSU)
R01UH0309EJ0500 Rev. 5.00 Page 1141 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
20.5 Interrupt Requests
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 20.7 lists the
interrupt sources.
When an interrupt condition shown in table 20.7 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DMAC data transfer.
Table 20.7 Interrupt Sources
Channel Abbreviation Interrupt Source Symbol Interrupt Condition
DMAC
Activation
0 SSERI0 Overrun error OEI0 (RIE = 1) • (ORER = 1) ⎯
Conflict error CEI0 (CEIE = 1) • (CE = 1) ⎯
SSRXI0 Receive data register full RXI0 (RIE = 1) • (RDRF = 1) ⎯
SSTXI0 Transmit data register empty TXI0 (TIE = 1) • (TDRE = 1) ⎯
Transmit end TEI0 (TEIE = 1) • (TEND = 1) ⎯