Datasheet

Section 20 Synchronous Serial Communication Unit (SSU)
Page 1140 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Yes
Start
Initial setting[1]
[2]
[1] Initial setting:
Specify the transmit/receive data format.
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE bit
is automatically cleared to 0 and transmission is started
by writing data to SSTDR.
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
[4]
[5]
[3]
Read TDRE in SSSR
TDRE = 1?
Yes
Yes
Yes
No
No
No
Write transmit data to SSTDR
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
Read SSSR
RDRF = 1?
ORER = 1?
Read receive data in SSRDR
RDRF automatically cleared
Consecutive data
transmission/reception?
Clear TE and RE in SSER to 0
Error processing
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Yes
No
No
Read TEND in SSSR
TEND = 1?
Yes
No
Has the 1 bit transfer
period elapsed?
Clear TEND in SSSR to 0
Figure 20.17 Flowchart Example of Simultaneous Transmission/Reception
(Clock Synchronous Communication Mode)