Datasheet

Section 3 MCU Operating Modes
R01UH0309EJ0500 Rev. 5.00 Page 85 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
3.2.2 System Control Register (SYSCR)
SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash
memory control registers, sets the external bus mode, and enables or disables on-chip RAM.
Bit Bit Name Initial Value R/W Descriptions
7, 6 ⎯ All 1 R/W Reserved
The initial value should not be modified.
5 MACS 0 R/W MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction performs non-saturation operation
1: MAC instruction performs saturation operation
4 ⎯ 0 R/W Reserved
The initial value should not be modified.
3 FLSHE 0 R/W Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMDBPR, and FLMSTR). If this
bit is set to 1, the flash memory control registers can
be read from and written to. If this bit is cleared to 0,
the flash memory control registers are not selected.
At this time, the contents of the flash memory control
registers are retained. 0 should be written to this bit in
LSIs other than the flash memory version.
0: Flash memory control registers are not selected for
addresses H'FFFEB0 to H'FFFEB3
1: Flash memory control registers are selected for
addresses H'FFFEB0 to H'FFFEB3
2 ⎯ 0 ⎯ Reserved
This bit is always read as 0 and cannot be modified.