Datasheet

Section 20 Synchronous Serial Communication Unit (SSU)
Page 1116 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
20.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 24-bit data length is selected, SSTDR0, SSTDR1, and SSTDR2 are
valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Be sure not to access to
invalid SSTDRs.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve
reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in
SSSR is set to 1.
Table 20.2 Correspondence Between DATS Bit Setting and SSTDR
DATS[1:0] (SSCRL[1:0])
SSTDR 00 01 10 11 (Setting Invalid)
0 Valid Valid Valid Valid
1 Invalid Valid Valid Valid
2 Invalid Invalid Valid Valid
3 Invalid Invalid Valid Invalid