Datasheet

Section 20 Synchronous Serial Communication Unit (SSU)
Page 1110 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
20.3.3 SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous
serial communication.
Bit Bit Name
Initial
Value R/W Description
7 MLS 0 R/W MSB First/LSB First Select
Selects that the serial data is transmitted in MSB first or
LSB first.
0: LSB first
1: MSB first
6 CPOS 0 R/W Clock Polarity Select
Selects the SSCK clock polarity.
0: High output in idle mode, and low output in active
mode
1: Low output in idle mode, and high output in active
mode
5 CPHS 0 R/W Clock Phase Select (Only for SSU Mode)
Selects the SSCK clock phase.
0: Data changes at the first edge.
1: Data is latched at the first edge.
4, 3 ⎯ All 0 R/W Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Clock Rate Select
Select the transfer clock rate when an internal clock is
selected.
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
000: Reserved
001: φ/4
010: φ/8
011: φ/16
100: φ/32
101: φ/64
110: φ/128
111: φ/256