Datasheet

Section 20 Synchronous Serial Communication Unit (SSU)
Page 1104 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 20.1 shows a block diagram of the SSU.
SSO
SSCK (External clock)
Module data bus
SSCRH
CEI
SSTRSR
Selector
RXI
SSCRL
SSMR
SSER
SSSR
Control circuit
Clock
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
Clock
selector
Internal data bus
Bus interface
SCS
SSI
Shiftout
Shiftin
OEI
TXI
TEI
[Legend]
SSCRH:
SSCRL:
SSCR2:
SSMR:
SSER:
SSSR:
SSTDR0 to SSTDR3:
SSRDR0 to SSRDR3:
SSTRSR:
SS control register H
SS control register L
SS control register 2
SS mode register
SS enable register
SS status register
SS transmit data registers 0 to 3
SS receive data registers 0 to 3
SS shift register
SSRDR 0
SSRDR 1
SSRDR 2
SSRDR 3
SSTDR 0
SSTDR 1
SSTDR 2
SSTDR 3
Figure 20.1 Block Diagram of SSU