Datasheet

Section 18 A/D Converter
Page 1082 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
18.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 18.6 shows the A/D conversion timing. Tables 18.5 and 18.6
show the A/D conversion time.
As shown in figure 18.6, the A/D conversion time (t
CONV
) includes the A/D conversion start delay
time (t
D
) and the input sampling time (t
SPL
). The length of t
D
varies depending on the timing of the
write access to ADCSR. The total conversion time therefore varies within the ranges indicated in
tables 18.5 and 18.6.
In scan mode, the values given in tables 18.5 and 18.6 apply to the first conversion time. The
values given in table 18.7 apply to the second and subsequent conversions. In either case, bit
EXCKS in ADCSR, and bits CKS1 and CKS0 in ADCR should be set so that the conversion time
is within the ranges indicated by the A/D conversion characteristics.
(1)
(2)
t
D
t
SPL
t
CONV
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t
D:
A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 18.6 A/D Conversion Timing