Datasheet

Section 2 CPU
R01UH0309EJ0500 Rev. 5.00 Page 81 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Exception
handling state
Bus-released state
Software standby
mode
Reset state
*
1
Sleep mode
Power down state
*
3
Program execution state
End of bus request
Bus request
RES = High
STBY = High,
RES = Low
Reset state
Hardware standby
mode
*
2
End of bus request
Bus request
Request for exception handling
Interrupt request
External interrupt request
SSBY = 0
SLEEP
instruction
SSBY = 1
SLEEP instruction
End of exception handling
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever the RES pin
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 24, Power-Down Modes.
Figure 2.13 State Transitions