Datasheet

Section 18 A/D Converter
R01UH0309EJ0500 Rev. 5.00 Page 1075 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name
Initial
Value R/W Description
3
2
CKS1
CKS0
0
0
R/W
R/W
Clock Select 1 and 0
These bits select the A/D conversion clock (ADCLK) and
specify the A/D conversion time in combination with the
EXCKS bit.
First select the A/D conversion time while ADST = 0 in
ADCSR and then set the mode of A/D conversion. Before
entering software standby mode or module stop state, set
these bits to B'11.
Set CKS1 and CKS0 bits appropriately so that the ADCLK
satisfies the conversion time.
EXCKS, CKS1, and CKS0
000: Setting prohibited
001: A/D conversion time = 268 states (max.) at ADCLK = φ/4
010: A/D conversion time = 138 states (max.) at ADCLK = φ/2
011: A/D conversion time = 73 states (max.) at ADCLK = φ
100: Setting prohibited
101: A/D conversion time = 172 states (max.) at ADCLK = φ/4
110: A/D conversion time = 90 states (max.) at ADCLK = φ/2
111: A/D conversion time = 49 states (max.) at ADCLK = φ
1 ADSTCLR 0 R/W A/D Start Clear
This bit enables or disables automatic clearing of the ADST
bit in scan mode.
0: The ADST bit is not automatically cleared to 0 in scan
mode.
1: The ADST bit is cleared to 0 upon completion of the A/D
conversion for all of the selected channels in scan mode.
[Legend]
x: Don't care
Notes: 1. If this bit is set the same as the TRGS_1, TRGS0, and EXTRGS bits in ADCR_0, the
A/D converter units 0 and 1 start A/D conversion by conversion start trigger from TPU
(units 0 and 1).
2. Setting prohibited in the H8S/2454 Group.