Datasheet

Page xi of xxx
Section 5 Interrupt Controller............................................................................109
5.1 Features.............................................................................................................................. 109
5.2 Input/Output Pins...............................................................................................................111
5.3 Register Descriptions......................................................................................................... 112
5.3.1 Interrupt Control Register (INTCR) ..................................................................... 113
5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN)............................................. 114
5.3.3 IRQ Enable Register (IER)................................................................................... 116
5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 118
5.3.5 IRQ Status Register (ISR)..................................................................................... 124
5.3.6 IRQ Pin Select Register (ITSR)............................................................................ 125
5.3.7 Software Standby Release IRQ Enable Register (SSIER).................................... 128
5.4 Interrupt Sources................................................................................................................ 129
5.4.1 External Interrupts ................................................................................................ 129
5.4.2 Internal Interrupts ................................................................................................. 130
5.5 Interrupt Exception Handling Vector Table....................................................................... 131
5.6 Interrupt Control Modes and Interrupt Operation.............................................................. 138
5.6.1 Interrupt Control Mode 0...................................................................................... 139
5.6.2 Interrupt Control Mode 2...................................................................................... 141
5.6.3 Interrupt Exception Handling Sequence ............................................................... 143
5.6.4 Interrupt Response Times ..................................................................................... 145
5.6.5 DTC and DMAC Activation by Interrupt............................................................. 146
5.7 Usage Notes ....................................................................................................................... 147
5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 147
5.7.2 Instructions that Disable Interrupts....................................................................... 148
5.7.3 Times when Interrupts are Disabled ..................................................................... 148
5.7.4 Interrupts during Execution of EEPMOV Instruction .......................................... 148
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting .............................................. 148
5.7.6 IRQ Status Register (ISR)..................................................................................... 149
Section 6 Bus Controller (BSC).........................................................................151
6.1 Features.............................................................................................................................. 151
6.2 Input/Output Pins...............................................................................................................154
6.3 Register Descriptions......................................................................................................... 157
6.3.1 Bus Width Control Register (ABWCR)................................................................ 158
6.3.2 Access State Control Register (ASTCR) .............................................................. 158
6.3.3 Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL) ........................................... 159
6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................. 165
6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 167