Datasheet

Section 18 A/D Converter
Page 1060 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Module data bus
Control circuit
Internal
data bus
10-bit A/D
Comparator
+
–
Sample-and-
hold circuit
ADI0 interrupt
signal
Bus interface
AVCC
Vref
AV
SS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADTRG0-A
Conversion start
trigger from
TPU (units 0, 1) or TMR
Successive approximation
register
Multiplexer
[Legend]
ADCR_0: A/D control register_0
ADCSR_0: A/D control/status register_0
ADDRA_0: A/D data register A_0
ADDRB_0: A/D data register B_0
ADDRC_0: A/D data register C_0
ADDRD_0: A/D data register D_0
ADDRE_0: A/D data register E_0
ADDRF_0: A/D data register F_0
ADDRG_0: A/D data register G_0
ADDRH_0: A/D data register H_0
ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADCSR_0 ADCR_0
ADTRG0-B
Figure 18.1 Block Diagram of A/D Converter Unit 0 (AD_0)