Datasheet

Section 17 I
2
C Bus Interface 2 (IIC2)
R01UH0309EJ0500 Rev. 5.00 Page 1041 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TDRE
TEND
ICDRS
ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
[3] Read ICDRR
1
A
2134567899
A
TRS
RDRF
SCL
(master output)
SDA
(master output)
SDA
(slave output)
Bit 7
Master transmit mode Master receive mode
Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
User
processing
Data 1
Data 1
Figure 17.7 Master Receive Mode Operation Timing 1