Datasheet

Section 2 CPU
R01UH0309EJ0500 Rev. 5.00 Page 77 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
2.7.8 Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode the memory operand is a longword operand, the first byte of which is assumed to
be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For
further details, see section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
Note: Normal mode is not available in this LSI.
Specified
by @aa:8
Specified
by @aa:8
Branch address
Branch address
Reserved
(a) Normal Mode
*
(a) Advanced Mode
Note: * Normal mode is not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Mode