Datasheet

Section 17 I
2
C Bus Interface 2 (IIC2)
R01UH0309EJ0500 Rev. 5.00 Page 1039 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TDRE
SCL
(master output)
SDA
(master output)
SDA
(slave output)
TEND
[5] Write data to ICDRT (third byte).
ICDRT
ICDRS
[2] Instruction of start
condition issuance
[3] Write data to ICDRT (first byte).
[4] Write data to ICDRT (second byte).
User
processing
1
Bit 7
Slave address
Address + R/W
Data 1
Data 1
Data 2
Address + R/W
Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2123456789
A
R/W
Figure 17.5 Master Transmit Mode Operation Timing 1
TDRE
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
TEND
ICDRT
ICDRS
19 23456789
A
A/A
SCL
(master output)
SDA
(master output)
SDA
(slave output)
Bit 7 Bit 6
Data n
Data n
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[5] Write data to ICDRT.
User
processing
Figure 17.6 Master Transmit Mode Operation Timing 2