Datasheet

Section 17 I
2
C Bus Interface 2 (IIC2)
R01UH0309EJ0500 Rev. 5.00 Page 1033 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
17.3.5 I
2
C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
Bit Bit Name Initial Value R/W Description
7 TDRE 0 R/W Transmit Data Register Empty
[Setting condition]
• When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty.
• When TRS has been set.
• When a start condition (including retransmission)
has been issued.
• When a transition from the receive mode to the
transmit mode has been made in the slave mode.
[Clearing conditions]
• When 0 is written in TDRE after reading
TDRE = 1.
• When data is written in ICDRT.
6 TEND 0 R/W Transmit End
[Setting conditions]
• When the ninth clock of SCL is rose while the
TDRE flag is 1.
[Clearing conditions]
• When 0 is written in TEND after reading TEND =
1.
• When data is written in ICDRT.
5 RDRF 0 R/W Receive Data Register Full
[Setting condition]
• When a received data is transferred from ICDRS
to ICDRR.
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF =
1.
• When data is read from ICDRR.