Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 32 MHz I/O number 96

Section 17 I

2

C Bus Interface 2 (IIC2)

Page 1022 of 1408 R01UH0309EJ0500 Rev. 5.00

Sep 24, 2012

H8S/2456, H8S/2456R, H8S/2454 Group

SCL

ICCRA

Transfer clock

generation

circuit

Address

comparator

Interrupt

generator

Interrupt request

Bus state

decision circuit

Arbitration

decision circuit

Noise canceler

Noise canceler

Output

control

Output

control

Transmission/

reception

control circuit

ICCRB

ICMR

ICSR

ICEIR

ICDRR

ICDRS

ICDRT

I

2

C bus control register A

I

2

C bus control register B

I

2

C mode register

I

2

C status register

I

2

C interrupt permission register

I

2

C transmission data register

I

2

C reception data register

I

2

C bus shift register

Slave address register

[Legend]

ICCRA:

ICCRB:

ICMR:

ICSR:

ICIER:

ICDRT:

ICDRR:

ICDRS:

SAR:

SAR

SDA

Internal data bus

Figure 17.1 Block Diagram of I

2

C Bus Interface 2