Datasheet

Section 16 USB Function Module (USB)
Page 1018 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.10.4 Assigning Interrupt Sources to EP0
The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must
be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations.
16.10.5 Clearing the FIFO When DMA Transfer is Enabled
EPDR1 cannot be cleared when DMA transfer for endpoint 1 is enabled (EP1DMAE in DMAR =
1). Cancel DMA transfer before clearing the register.
16.10.6 Notes on TR Interrupt
Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,
EP2, and EP3.
The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent
from the USB host. However, at the timing shown in figure 16.25, multiple TR interrupts occur
successively. Take appropriate measures against malfunction in such a case.
Note: This module determines whether to return NAK if the FIFO of the target EP has no data
when receiving the IN token, but the TR interrupt flag is set after a NAK handshake is
sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is
set again.
CPU
Host IN token IN token IN token
Sets TR flag
(Sets the flag again)
Sets TR flag
Determines whether
to return NAK. Transmits data
TR interrupt routine
Clear
TR flag
Writes
transmit data
TRG.
PKTE
TR interrupt routine
USB
NAK
Determines whether
to return NAK.
NAK
ACK
Figure 16.25 TR Interrupt Flag Set Timing