Datasheet

Section 16 USB Function Module (USB)
Page 1006 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(1) Dual FIFOs (EP2)
EP2 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being
aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For
example, even if both FIFOs are empty, it is not possible to perform EP2 PKTE at one time after
consecutively writing 128 bytes of data. EP2 PKTE must be performed for each 64-byte write.
When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first
IN token, an EP2 TR bit interrupts in IFR2 is requested. With this interrupt, 1 is written to the EP2
EMPTYE bit in IER2, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are
empty, and so an EP2 FIFO empty interrupt is generated immediately.
The data to be transmitted is written to the data register using this interrupt. After the first transmit
data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to
the other FIFO immediately. When both FIFOs are full, EP2 EMPTYE is cleared to 0. If at least
one FIFO is empty, the EP2 EMPTY bit in IFR2 is set to 1. When ACK is returned from the host
after data transmission is completed, the FIFO used in the data transmission becomes empty. If the
other FIFO contains valid transmit data at this time, transmission can be continued.
When transmission of all data has been completed, write 0 to the EP2 EMPTYE bit in IER2 and
disable interrupt requests.