Datasheet

Section 16 USB Function Module (USB)
Page 976 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name
Initial
Value R/W Description
0 EP1 DMAE 0 R/W EP1 DMA Transfer Enable
When this bit is set, a DMA transfer request (USB
INTN0) is asserted and DMA transfer is enabled from
the endpoint 1 receive FIFO buffer to memory. If there is
at least one byte of receive data in the FIFO buffer, the
DMA transfer request (USB INTN0) is asserted. In DMA
transfer, when all the received data is read, EP1 is
automatically read and the completion trigger operates.
EP1-related interrupt requests to the CPU are not
automatically masked.
• Operating procedure:
1. Write of 1 to the EP1 DMAE bit in DMA
2. Set the DMAC to activate through DREQ0
(USB INTN0)
3. Transfer count setting in the DMAC
4. DMAC activation
5. DMA transfer
6. DMA transfer end interrupt generated
See section 16.8.3, DMA Transfer for Endpoints 1and 4.