Datasheet

Section 16 USB Function Module (USB)
Page 974 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name
Initial
Value R/W Description
3
⎯
0
⎯ Reserved
This bit is always read as 0. The write value should
always be 0.
2 EP3 STLST 0 R EP3 internal stall state
1 EP2 STLST 0 R EP2 internal stall state
0 EP1 STLST 0 R EP1 internal stall state
16.3.27 DMA Transfer Setting Register (DMAR)
DMA transfer can be carried out between the data registers for endpoints 1 and 2 and memory by
means of the on-chip direct memory access controller (DMAC). Dual address transfer is
performed in bytes. To start DMA transfer, DMAC settings must be made in addition to the
settings in this register.
Bit Bit Name
Initial
Value R/W Description
7
6
5
⎯
⎯
⎯
0
0
0
⎯
⎯
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
4 ⎯ 0 R/W
Reserved
The write value should always be 0.
3 ⎯ 0 R/W
Reserved
The write value should always be 0.
2 ⎯ 0 ⎯
Reserved
This bit is always read as 0. The write value should
always be 0.