Datasheet
Section 16 USB Function Module (USB)
R01UH0309EJ0500 Rev. 5.00 Page 973 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.26 Stall Status Register 1 (STLSR1)
Bits 2 to 0 in STLSR1 are status bits that indicate the internal stall state of each endpoint (internal
status bits shown in figures 16.19 and 16.20). When a bit is 1, the corresponding endpoint is in
stall state. When a bit is 0, the corresponding endpoint is in normal operation state. Since these
bits are status bits, they cannot be cleared.
Bits 6 to 4 in STLSR1 are used to enable automatic stall clear for each endpoint.
Bit Bit Name
Initial
Value R/W Description
7 ⎯
0
⎯ Reserved
This bit is always read as 0. The write value should
always be 0.
6 EP3 ASCE
0
R/W
EP3 Automatic Stall Clear Enable
Setting the EP3 ASCE bit to 1 automatically clears the
EP3 stall setting bit (the EP3 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP3 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP3 ASCE bit should be set to 1
before the EP3 STLS bit in EPSTL1 is set to 1.
5 EP2 ASCE
0
R/W
EP2 Automatic Stall Clear Enable
Setting the EP2 ASCE bit to 1 automatically clears the
EP2 stall setting bit (the EP2 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP2 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP2 ASCE bit should be set to 1
before the EP2 STLS bit in EPSTL1 is set to 1.
4 EP1 ASCE
0
R/W
EP1 Automatic Stall Clear Enable
Setting the EP1 ASCE bit to 1 automatically clears the
EP1 stall setting bit (the EP1 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP1 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP1 ASCE bit should be set to 1
before the EP1 STLS bit in EPSTL1 is set to 1.