Datasheet

Section 16 USB Function Module (USB)
Page 972 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.25 Endpoint Stall Register 1 (EPSTL1)
Bits 2 to 0 in EPSTL1 are used to forcibly stall the corresponding endpoints on the application
side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. Bits 6
to 4 are used to clear the stall settings for the endpoints (bits 2 to 0). Writing 1 to the stall setting
bit and stall clear bit for an endpoint at the same time is prohibited.
For detailed operation, see section 16.7, Stall Operations.
Bit Bit Name
Initial
Value R/W Description
7 ⎯
0
⎯ Reserved
This bit is always read as 0. The write value should
always be 0.
6 EP3 STLC 0 W EP3 Stall Clear
Writing 1 to this bit clears the EP3 STLS bit to 0.
Writing 0 is ignored.
5 EP2 STLC 0 W EP2 Stall Clear
Writing 1 to this bit clears the EP2 STLS bit to 0.
Writing 0 is ignored.
4 EP1 STLC 0 W EP1 Stall Clear
Writing 1 to this bit clears the EP1 STLS bit to 0.
Writing 0 is ignored.
3 ⎯
0
⎯ Reserved
This bit is always read as 0. The write value should
always be 0.
2 EP3 STLS 0 R/W EP3 Stall Setting
Writing 1 to this bit specifies a stall for EP3. Writing 0
is ignored.
1 EP2 STLS 0 R/W EP2 Stall Setting
Writing 1 to this bit specifies a stall for EP2. Writing 0
is ignored.
0 EP1 STLS 0 R/W EP1 Stall Setting
Writing 1 to this bit specifies a stall for EP1. Writing 0
is ignored.