Datasheet

Section 16 USB Function Module (USB)
R01UH0309EJ0500 Rev. 5.00 Page 971 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.24 Endpoint Stall Register 0 (EPSTL0)
Bit 0 in EPSTL0 is used to forcibly stall endpoint 0 on the application side. While the bit is set to
1, the corresponding endpoint returns a stall handshake to the host. Bit 4 is used to clear the stall
setting in bit 0. Writing 1 to the EP0 stall setting bit and stall clear bit at the same time is
prohibited.
The stall bit for endpoint 0 is cleared automatically on reception of 8-byte setup command data for
which decoding is performed by firmware the EP0 STLS bit is cleared. When the SETUPTS flag
in the IFR1 is set to 1, writing 1 to the EP0 STLS bit is ignored. For detailed operation, see section
16.7, Stall Operations.
Bit Bit Name
Initial
Value R/W Description
7
6
5
⎯
⎯
⎯
0
0
0
⎯
⎯
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
4 EP0 STLC 0 W EP0 Stall Clear
Writing 1 to this bit clears the EP0 STLS bit to 0.
Writing 0 is ignored.
3
2
1
⎯
⎯
⎯
0
0
0
⎯
⎯
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
0 EP0 STLS 0 R/W EP0 Stall Setting
Writing 1 to this bit specifies a stall for EP0. Writing 0
is ignored.