Datasheet

Section 16 USB Function Module (USB)
Page 970 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.23 FIFO Clear Register 1 (FCLR1)
FCLR1 is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
⎯
⎯
⎯
⎯
⎯
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
Reserved
The write value should always be 0.
2 EP3 CLR 0 W EP3 Clear
Writing 1 to this bit initializes the endpoint 3 transmit
FIFO buffer.
1 EP2 CLR 0 W EP2 Clear
Writing 1 to this bit initializes both sides of the
endpoint 2 transmit FIFO buffer.
0 EP1 CLR 0 W EP1 Clear
Writing 1 to this bit initializes both sides of the
endpoint 1 receive FIFO buffer.